Field of the Invention
The invention relates in general to a multimedia signal processing technology, and more particularly, to a decompression technology for the audio video coding standard (AVS).
Description of the Related Art
Digital television broadcasting has matured and become prevalent with the ever-improving communication technologies. In addition to being transmitted through cables, digital television signals may be propagated in form of wireless signals via base stations or artificial satellites. To satisfy demands on enhanced image quality and reduced transmission data amount, a transmitting end usually encodes and decompresses audio/video signals to be transmitted. Correspondingly, a receiving end needs to correctly decode and decompress the received signals in order to restore the audio/video signals.
The audio video coding standard (AVS) prevalent in the Mainland China adopts advanced entropy coding to process audio/video data. Implementation details of this technique can be referred from the U.S. Pat. No. 7,808,406 and technical documentations provided by the AVS team. Such solution significantly increases the audio/video compression efficiency. According to specifications of current AVS technical documentations, a binary arithmetic coding engine at the receiving end needs to perform a decoding procedure according to pseudo codes shown in FIG. 1(A) and FIG. 1(B). The procedure may be represented as flowcharts depicted in FIG. 2(A) and FIG. 2(B). As known to one person having ordinary skill in the art, the binary arithmetic coding is an iterative process having an input referred to as an offset. By identifying a corresponding relationship between sizes of the offset and a range, it can be determined whether a current symbol to be decoded is a most probable symbol (MPS) or a least probable symbol (LPS).
In the decoding process shown in FIG. 2(A) and FIG. 2(B), two main variables associated with the range are a range shift value (denoted as rS1 and rS2 in the pseudo codes in FIG. 1(A) and FIG. 1(B), where rS1 represents an original input value and rS2 represents an updated value), and a valid range value (denoted as rT1 and rT2 in the pseudo codes, where rT1 represents an original input value and rT2 represents an updated value). Two main variables associated with the offset are an offset shift value (denoted as valueS in the pseudo codes) and a valid offset value (denoted as valueT in the pseudo codes). In practice, a data length that an arithmetic coding engine is capable of processing is limited. Specified by current AVS technical documentations, an arithmetic coding engine is required to set both of the range shift value and the valid range value to 8 binary bits. On the other hand, the offset shift value and the valid offset value need to be set to 32 binary bits and 9 binary bits, respectively. Further, in the pseudo codes in FIG. 1(A) and FIG. 1(B), a probability of the MPS is denoted as IgPmps. The range of the LPS is denoted as tRlps. The denotation sFlag represents a determination flag.
A pseudo code section 11 in FIG. 1(A), corresponding to step S201, provides a main function of fetching a last updated context model of a previous decoding procedure, accordingly determines whether the MPS is “0” or “1” in a current decoding procedure, and further determines the probability of the MPS. A pseudo code section 12 in FIG. 1(A), corresponding to step S202, is depicted in detail as sub-steps S202A to S202G in FIG. 3(A). A main function of step S202 is to update the range shift value and the valid range value according to an old range and the probability of the MPS, and to determine whether the determination flag is “0” or “1”.
A pseudo code section 13 in FIG. 1(B) corresponds to steps S203 to S210. When: 1) the range shift value is greater than the offset shift value, or 2) the range shift value is equal to the offset shift value and the valid offset value is greater than or equal to the valid range value, subsequent steps S204 to S219 are performed. When a determination result of step S203 is affirmative, it means that a decoding result to be outputted by the current decoding procedure is an LPS. A main function of steps S205 to S210 is to determine an LPS range value and the valid offset value. A pseudo section 14 in FIG. 1(B), corresponding to steps S211 to S215, perform a main function of renormalization to render the LPS range value to be greater than or equal to 256. Meanwhile, the content of the valid offset value is correspondingly adjusted. A pseudo code section 15 in FIG. 1(B), corresponding to steps S216 to S218, provide a main function of pre-fetching a subsequent offset for the use of a next round of decoding procedure. According to specifications of current AVS technical documentations, given it is determined that the current valid offset value is smaller than 256, the pre-fetching step S217 is iterated to continue accumulating the offset shift value.
When the determination result of step S203 is negative, it means that the decoding result to be outputted by the current decoding procedure is an MPS. A pseudo code section 16 in FIG. 1(B), corresponding to step S291, performs a main function of setting the decoding result as an MPS. Step S292 and step S219 in FIG. 2(B), both corresponding to a pseudo code section 17 in FIG. 1(B), serve a main function of updating the context model and feeding back the decoding result.
In the above decoding procedure, the pseudo code section 15 corresponding to the pre-fetching steps S216 to S218 contain certain drawbacks to be described below. In step S203 in FIG. 1(A), the offset shift value and the range shift are compared with each other. When the offset shift value is greater than the range shift value, steps S291 and S292 are performed. As previously stated, the length of the offset shift value is set to 32 bits, and the length of the range shift value is set to 8 bits. In other words, theoretically, a maximum value of the offset shift value may reach as high as (232−1), whereas a maximum value of the range shift value can reach only (28−1=255). According to the decoding procedure in FIG. 2(A) to FIG. 2(B) and FIG. 3(A), only when the offset shift value does not exceed 254, the range shift value can then catch up with the offset shift value via step S202E to maintain a consistent comparison basis for the valid offset value and the valid range value. However, a currently known offset inputted into an arithmetic coding engine of a receiving end may be more than 254 continuous bit “0”, in a way that the pre-fetching step S217 is repeatedly performed for over 254 times and the offset shift value is accumulated to a value higher than 254. It should be noted that, as shown in FIG. 2(A) and FIG. 2(B), only when the determination result of step S203 is affirmative, step S215 of resetting the offset shift value to zero can then be performed. As it is impossible that the range shift value be higher than the offset shift value that is accumulated to a value higher than 255, the determination result of step S203 constantly remains negative. In practice, when the offset shift value exceeds 254, the entire decoding procedure may collapse and an erroneous decoding result is outputted.
The same situation may also occur in an initialization procedure of 2the offset shift value and the valid offset value in FIG. 3(B). Comparing FIG. 3(B) and FIG. 2(B), it is observed that steps S303 to S305 are identical to the pre-fetching steps S216 to S218. That is to say, it is also possible that the offset shift value be accumulated to higher than 254, resulting in the above issue of a collapsed decoding process.
The current bit pre-fetching solution further suffers from other drawbacks. As shown in FIG. 2(B), once having entered step S216, steps S216 and S217 are iterated until the determination result of step S216 is negative. In practice, a circuit that performs step S217 may fetch subsequent offsets from an external memory or a front-end circuit via a bus. When the bus, the external memory or the front-end circuit is in a busy status (e.g., when its utilization permission is occupied by other circuits), the circuit that performs step S217 needs to wait. If the wait period gets too long, the entire decoding procedure inevitably comes to a standstill at step S217 and cannot be further performed, leading to degraded performance of an AVS decoding end.